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CY2030
USB, Audio, and I/O Clock Generator for Intel 82440LX Chipset
Features
* USB, Audio, and I/O clock generator for most motherboards using 5th or 6th generation processors. Can also be used for peripheral systems. * Two copies of 48 MHz USB clocks * One copy of 24 MHz I/O clock * Audio support for 33.8688 MHz, 24.576 MHz, 16.9344 MHz and 12.288 MHz, pin-selectable * Three copies of Ref. clock @ 14.318 MHz * 14.318 MHz reference input * Ability to three-state all outputs * Test mode support * Output duty cycle 45% min. to 55% max. * Available in 20-pin SSOP packages * 3.3V operation * Internal pull-up resistors on S0, S1, and OE inputs
Functional Description
The CY2030 is a peripheral clock generator for most motherboards using fifth and sixth generation processors. The device outputs two copies of a 48 MHz USB clock, as well as one copy of a 24 MHz I/O clock, both of which meet Intel's accuracy, drive, and jitter requirements. Additionally, the part drives two audio clock outputs at 2X and 1X frequencies respectively. These audio clocks support all frequencies that are required by CODECs and FM synthesizers. Finally, the part outputs three reference clocks at 14.318 MHz, which can be used to drive ISA slots, graphics accelerators, and other devices requiring this frequency. The CY2030 can be used with the CY2275-1 and CY2276-1 (which are CPU, AGP, PCI, and SDRAM clock generators) to provide a complete clock solution for PC motherboards. The CY2030 accepts a 14.318 MHz reference signal as its input. The CY2030 has two PLLs, one of which generates the audio clocks, and the other generates the Universal Serial Bus (USB) and I/O clocks. The CY2030 runs off a 3.3V supply.
Logic Block Diagram
REF0 (14.318 MHz) REF1 (14.318 MHz) REF2 (14.318 MHz) SYS PLL
(96 MHz)
Pin Configuration
Top View SSOP
VDD XTALIN XTALOUT VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 REF2 REF1 VDD REF0 VSS USBCLK0 USBCLK1 VDD IOCLK VSS
XTALIN XTALOUT
14.318 MHz OSC.
2:1
/2
USBCLK0 (48 MHz) USBCLK1 (48 MHz) /2 IOCLK (24 MHz)
OE 2XAUDIO AUDIO VDD SEL0 SEL1
Audio PLL
2:1
/2 /2
2XAUDIO
ROM
AUDIO
SEL0 SEL1
OE
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 January 10, 1997 - Revised July 1, 1997
CY2030
Pin Summary
Name VDD XTALIN VSS OE 2XAUDIO AUDIO VDD SEL0 SEL1 VSS IOCLK VDD USBCLK1 USBCLK0 VSS REF0 VDD REF1 REF2
[1, 2]
Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Description 3.3V voltage supply Reference crystal input, typically 14.318 MHz Reference crystal feedback Ground Output Enable, active HIGH (internal pull-up resistor to VDD). Three-states all outputs when driven LOW. 2XAudio clock output, at 33.8688 MHz or 24.576 MHz (See function table below) Audio clock output, at 16.9344 MHz or 12.288 MHz (See function table below) 3.3V voltage supply Audio clock select input, bit 0 (internal pull-up resistor to VDD) Audio clock select input, bit 1 (internal pull-up resistor to VDD) Ground I/O clock output (24.0 MHz) 3.3V Voltage supply USB clock output (48.0 MHz) USB clock output (48.0 MHz) Ground REF clock output for ISA slots, drives 45 pF loads (14.318 MHz) 3.3V voltage supply Reference clock output (14.318 MHz) Reference clock output (14.318 MHz)
XTALOUT[1]
Function Table
OE 0 1 1 1 1 SEL1 X 0 0 1 1 SEL0 X 0 1 0 1 XTALIN 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 2XAudio High-Z XTALIN/2
[3]
Audio High-Z XTALIN/4
[3]
REF [0:2] High-Z XTALIN
[3]
USBCLK [0:1] High-Z XTALIN/2 48 MHz 48 MHz 48 MHz
[3]
IOCLK High-Z XTALIN/4[3] 24 MHz 24 MHz 24 MHz
24.576 MHz 33.8688 MHz Low
12.288 MHz 16.9344 MHz Low
14.318 MHz 14.318 MHz 14.318 MHz
Actual Frequency Values
Clock USBCLK IOCLK 2XAUDIO 2XAUDIO AUDIO AUDIO REF 48.0 24.0 33.8688 24.576 16.9344 12.288 14.318 Target Frequency (MHz) 48.008 24.004 33.8680 24.5795 16.9340 12.2898 14.318 Actual Frequency (MHz) 167 167 -24 144 -24 144 0 PPM
Notes: 1. XTALIN and XTALOUT do not have internal compensation capacitors. Therefore, if an external crystal is used with the device, external compensation capacitors are required to match the load capacitance of the crystal. 2. If the reference is an external clock, it should be driven on the XTALIN input, and XTALOUT must be left floating. 3. Intel Test Mode
2
CY2030
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................-0.5 to +4.6V Input Voltage.............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing)... -65C to +150C Max. Soldering Temperature (10 sec)...................... +260C Junction Temperature .............................................. +150C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
Operating Conditions[4]
Parameter VDD TA CL Description Supply Voltage, 3.3V Operating Temperature, Ambient Capacitive Load on All Clock Outputs except REF0 REF0 Reference Clock Input Frequency Min. 3.135 0 10 20 14.318 Max. 3.465 70 20 45 14.318 Unit V C pF
f(REF)
MHz
Electrical Characteristics VDD = 3.135V to 3.465V, TA = 0C to +70C
Parameter VIH VIL VOH[5] VOH[5] VOL[5] VOL[5] IIH IIL IOZ IDD Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage High-level Output Voltage Low-level Output Voltage Low-level Output Voltage Input High Current Input Low Current Output Leakage Current Power Supply Current Test Conditions Except Crystal Inputs Except Crystal Inputs VDD = VDD Min. VDD = VDD Min. VDD = VDD Min. VDD = VDD Min. VIH = VDD VIL = 0V Three-state VDD = 3.465V, VIN = 0 or V DD -10 IOH = -15 mA IOH = -38 mA IOL = 8 mA IOL = 22 mA All outputs except REF0 REF0 All outputs except REF0 REF0 5 100 +10 50 A A A mA 0.4 V 2.4 Min. 2.0 0.8 Max. Unit V V V
Switching Characteristics[5, 6]
Parameter t1 t2 t3 t2 t3 t4 All REF0 REF0 All Clock outputs except REF0 All Clock outputs except REF0 USBCLK, IOCLK Output Description Output Duty Cycle
[7]
Test Conditions t1 = t1A / t1B Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V Measured at 1.5V
Min. 45%
Max. 55% 2.0 2.0 4 4 500
Unit ns ns ns ns ps
REF0 Clock Rise Time REF0 Clock Fall Time Clock Rise Time Clock Fall Time Cycle-Cycle Clock Jitter
Notes: 4. Electrical parameters are guaranteed with these operating conditions. 5. Guaranteed by design and characterization, not 100% tested in production. 6. All parameters specified with outputs fully loaded. 7. Duty cycle is measured at 1.5V.
3
CY2030
Switching Waveforms
Duty Cycle Timing
t1B
t1A 1.5V 1.5V
1.5V
All Outputs Rise/Fall Time
2.0V 0.8V t2 2.0V 0.8V t2 VDD 0.8V 0V
OUTPUT
4
CY2030
Applications Information
Clock traces must be terminated with either series or parallel termination, as they are normally done. Additionally, the CY2030 does not have crystal load matching capacitors internal to the device, and therefore, external capacitors will be needed when using the device with an external crystal.
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board V DD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
5
CY2030
Test Circuit
VDD
1 0.1 F 4
18 0.1 F 16
8 0.1 F 11
13 0.1 F OUTPUTS CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Ordering Information
Ordering Code CY2030PVC-1 Document #: 38-00560-B Package Name O20 Package Type 20-Pin SSOP Operating Range Commercial
6
CY2030
Package Diagram
All Dimensions in mm. 20-Pin Shrunk Small Outline Package O20
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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